FPGA Implementation

Written On: 06 Apr 2026 - dev-blog | cpu-dev | vlsi

Successfully synthesised VR16 on the Terasic DE0 FPGA!

image credits: https://in.pinterest.com/pin/14073817581298704/

You heard it correctly!

The VR16 journey was utilised as my final year project so I went with that hehe.

This will be a short read but yeah.

College asked some sort of hardware implementation so I borrowed the FPGA from a friend of mine and did the entire synthesis it’s quite cool.

Here’s a small video!

for loop execution!

Yeah it was quite cool to do this genuinely seeing my CPU running in real time!

I used the Terasic DE0 board which uses a Cyclone III chip, quite old but this was MORE than enough. I barely used like 7% of the logic elements present so it was cool.

Implementation wise few changes

So since there is an in-built 50Mhz clock generator, had to use a clock divider circuit to reduce the speed so that we could see the output physically on the 7-segment displays.

Then since I have 4 registers, used the buttons to switch between registers to show values present in each of them. Quite cool stuff.

Yeah that’s it

---