RTL is complete!

Long needed and awaited update on the cpu hehe!

image credits: https://in.pinterest.com/pin/75364993760206538/

The fix for the issue spoken in old blogs

Yes you heard that exactly, RTL is finally complete! After all it was genuinely a silly mistake that I made. All I had to do was change few modules from sequential to combinational

This one particular line screwed me over big time:

// before
always @ (posedge clk or posedge reset)

Once I changed this I still faced few issues. That’s where my dear friend mr. saint man came in and fixed most of my cpu.

Fixing involved fixing EXTREMELY SILLY MISTAKES.

See once I had changed the modules to combinational, I had to change the assignments to blocking, which was what mr saint man did. Apart from that, he also made the toolchain complete and a proper CLI tool which I had planned to do.

He had overall kept the fundamentals I had built and made it just better.

I had severe imposter syndrome after seeing his PR cause madlad went ahead and made 80 something commits

Furthermore

image credits: https://in.pinterest.com/pin/94646029665710655/

This was time for the king (me) to rise and finish the instruction set and finish the CPU.

I was looking forward to incorporate delete and finish up jump. Even then I had space for one more instruction and I didn’t know what to do with it.

Once BASIC RTL was done and I tested out Saint bro’s PR the ENTIRE CPU felt like a basic calculator. Cause it just did all the basic arithmetic and logic stuff. Nothing special and my sense of achievement was just “meh”

That’s when I wanted to do something and I whipped up two new instruction:

• shift
• cjmp

Shift and conditional jumps were two new instructions I then went ahead and implemented and uh finished. The assembler also now supports both these instructions.

Future of this CPU

Well, the old documentation page which is this btw stated that I would be doing a SoC. Like genuinely a full blown SoC (check old commit of the website).

I must’ve been delusional when I said that, but in reality that’s not going to happen.

I’m also not pipelining this CPU cause there is this FSM state that I implemented for fixing a bug with cjmp not working properly named REFETCH.

It’s something that just works. It’s not proper in terms of professionalism or industry.

However, I have to implement this in a FPGA for my final year project as this is what I’ve submitted to my college. I’m using the Terasic DE0 Cyclone III for this. Quite cool, cause this is also my first time working with FPGAs.

I will however go on and finish up the Physical Design for this and generate a GDSII file at some point this year. When? Don’t ask, I have bunch of other committments for me to fulfill for my ownself to be happy.

I’ll share it at one point

I’ll learn pipelining (theoratically I’m aware) by just implementing the RISC-V. I realised later on that VR16-ISA is basically a run-down version of RISC-V.

I mean, hey games the game. I wanted something unique and different, I didn’t have an application but yeah.

All that is pending after I finish the FPGA implementation is:

• add pseudo instructions like del and mov in both assembler and compiler.
• add while loops and if-else support too.

Misc.

I know this doesn’t come under this blog, but I was thinking of you know, writing a simple decoder for amd64