VR16 CPU 🔗

This is a simple 16-bit RISC CPU built from scratch. This is the full-on documentation for the VR16 CPU (which is the name for it).

VR16 runs on it’s own instruction set called VR16-ISA. At the moment, this is at version 0.1.

THIS IS NOT A RISC-V CPU, but a RISC one.

GitHub repository: Link

NOTE: These documentation will keep changing, the proper STABLE release will be showcased, this is just the TESTING version for now.

Specifications 🔗

The following mention the specifications of VR16:

• 16-bit CPU (this is the 2nd time I’ve mentioned that lol)
• has 4 general purpose registers
• supports immediate values

Documentation 🔗

• Working

• Instruction Set

• Assembler && VR-ASM Docs

Setup 🔗

1. Clone the repo using:

   git clone git@github.com:bsod2528/cpu.git
   

2. Write your own vr-asm asm files and store in under the asm source files/.
3. Then do the below commands.

   py -m venv env
   cd env/Scripts
   activate
   cd ..\..
   pip install -r requirements.txt
   

4. In order to create the imem (instruction memory file), use the assembler for that.
5. Edit the assembler.py to read from your .asm file.
6. Run

   py assembler.py
   

7. To run the RTL simulation as of now there are two ways.
   • Windows: Download AMD Vivado or Intel Quartus to run the simulation.
   • Linux: Download GTKWave and Iverilog.
     • Further compile the verilog code using compile.sh and run sim.sh

Roadmap 🔗

So at the moment, work for the front-end is happening. Once this is done:

1. physical design will be done, i.e., back-end all using OpenROAD.
2. further expansion of front-end into a 32-bit SoC
3. further expansion of back-end for the entire SoC.
4. hopefully, port this into an FPGA and run instructions.

Misc. 🔗

The below list out all the dev-blogs I’ve written while developing this:

• VR16 - ALU I HATE YOU!!!! — Apr 02, 2025

• VR16 Devblog 1 — Mar 28, 2025

tree /f 🔗

I’m bored so here you go :D

│ .gitignore
│ CHANGELOG.md
│ compile.sh
│ ISA.md
│ LICENSE
│ README.md
│ requirements.txt
│ sim.sh
│ 
├───asm source files/
│ 		add.asm
│ 		and_gate.asm
│ 		delete_from_reg.asm
│ 		not_gate.asm
│ 		sub.asm
├───assembler/
│ 	│ 	assembler.py
│ 	│ 	baseclass.py
│ 	│ 	extractor.py
│ 	│
│ 	└───env/
│ 
├───design sources/
│ 		alu.v
│ 		control_unit.v
│ 		gp_registers.v
│ 		instruction_decoder.v
│ 		instruction_memory.v
│ 		program_counter.v
│ 
├───memory files/
│ 		imem.mem
│ 		imem.txt
│ 		imem_two.txt
│ 		write_imem.mem
└───testbenches/
		tb_cu.v
		tb_gpr.v
		tb_id.v
		tb_imem.v
		tb_pc.v