VR16 CPU 🔗

This is a simple 16-bit RISC CPU built from scratch. This is the full-on documentation for the VR16 CPU (which is the name for it).

VR16 runs on it’s own instruction set called VR16-ISA. At the moment, this is at version 0.1.

THIS IS NOT A RISC-V CPU, but a RISC one.

GitHub repository: Link

NOTE: These documentation will keep changing, the proper STABLE release will be showcased, this is just the TESTING version for now.

Specifications 🔗

The following mention the specifications of VR16:

• 16-bit CPU (this is the 2nd time I’ve mentioned that lol)
• has 4 general purpose registers
• supports immediate values

Documentation 🔗

• Working

• Instruction Set

Roadmap 🔗

So at the moment, work for the front-end is happening. Once this is done:

1. assembler will be written so that instructions don’t have to be manually written as 0000111100001111 for example.
2. physical design will be done, i.e., back-end all using open source tools.
3. further expansion of front-end into a 32-bit SoC
4. further expansion of back-end for the entire SoC.
5. hopefully, port this into an FPGA and run instructions.

Misc. 🔗

The below list out all the dev-blogs I’ve written while developing this:

• VR16 - ALU I HATE YOU!!!! — Apr 02, 2025

• VR16 Devblog 1 — Mar 28, 2025

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