VR16 CPU 🔗

Updated based on: a03ddea555b00e2594c6f16772c364bf0e9e9897

This is a simple 16-bit RISC CPU built from scratch. This is the full-on documentation for the VR16 CPU (which is the name for it).

VR16 runs on it’s own instruction set called VR16-ISA. At the moment, this is at version alpha.

This is not a RISC-V CPU, but a RISC one.

GitHub repository: Link

NOTE: These documentation will keep changing, the proper STABLE release will be showcased, this is just the TESTING version for now.

Specifications 🔗

The following mention the specifications of VR16:

• single-stage, multi-cycle cpu
• 16-bit cpu (this is the 2nd time I’ve mentioned that lol)
• has 4 general purpose registers
• supports immediate values
• basic branching of 1 command supported

Documentation Links 🔗

• Working

• Instruction Set

• Assembler && VR-ASM Docs

• VRScript

Setup 🔗

On how to run this project in your local machine.

Windows 🔗

1. Install WSL and install gtkwave and iverilog.
2. Setup venv in root directory.
3. Run ./compile.sh and then ./sim.sh to view the rtl waveforms.

Linux 🔗

1. Install gtkwave and iverilog.
2. Setup venv in root directory.
3. Run ./compile.sh and then ./sim.sh to view the rtl waveforms.

Roadmap 🔗

So at the moment, work for the front-end is happening. Once this is done:

1. pipeline the entire cpu.
2. physical design will be done, i.e., back-end all using OpenROAD. <!– 2. further expansion of front-end into a 32-bit SoC
3. further expansion of back-end for the entire SoC.
4. hopefully, port this into an FPGA and run instructions. –>

Misc. 🔗

The below list out all the dev-blogs I’ve written while developing this:

• VR16 Update - Jul 02, 2025

• VR16 - ALU I HATE YOU!!!! - Apr 02, 2025

• VR16 Devblog 1 - Mar 28, 2025

tree /f 🔗

I’m bored so here you go :D

│   .gitignore
│   CHANGELOG.md
│   compile.sh
│   ISA.md
│   LICENSE
│   README.md
│   requirements.txt
│   sim.sh
│
├───examples
│   ├───vr-asm
│   │       add.asm
│   │       and_gate.asm
│   │       compiled.asm
│   │       delete_from_reg.asm
│   │       not_gate.asm
│   │       sub.asm
│   │
│   └───vrscript
│           add.vrs
│
├───mem
│       imem.mem
│       imem.txt
│       imem_two.txt
│       write_imem.mem
│
├───src
│   ├───backend
│   │       coming soon
│   │
│   └───frontend
│       │   vr16_cpu.v
│       │
│       ├───rtl
│       │       alu.v
│       │       control_unit.sv
│       │       gp_registers.v
│       │       instruction_decoder.v
│       │       instruction_memory.v
│       │       program_counter.v
│       │
│       └───tb
│               tb_cpu.v
│               tb_cu.v
│               tb_gpr.v
│               tb_id.v
│               tb_imem.v
│               tb_pc.v
│
└───sw
    ├───assembler
    │       assembler.py
    │       baseclass.py
    │       extractor.py
    │
    └───compiler
            compiler.py
            extractor.py