VR16 CPU Home Page

Ideal working of VR16 🔗

So, it all starts with a simple clock pulse.

1. Program counter’s counter_reg increments on the 1st clock pulse.
   • This essentially points to a memory address.
2. Instruction memory holds all the instructions.
   • A simple .mem file for now.
3. Instruction decoder further parses all the information and sends out data accordingly.
4. Control unit takes care of reading and writing and letting the ALU to work.
5. ALU does arithmetic and logical operations alone.
6. Results are further stored in 1 of 4 general purpose registers [R0, R1, R2, R3]

In reality what’s the case? 🔗

As of this commit: f6c446e6df563b7e4b69a8135304f4a15109e210, the above mentioned doesn’t happen.

The part where control unit takes care of reading and writing is yet to be implemented.

All parts have been implemented, yet the “connecting” between all the parts is yet to be done alone. As of date April 8th 2025, I’ve had my CAN YOU HEAR THE MUSIC MOMENT!!!!.

So soon enough this page will be updated, and the code will be updated to support connection.

As of the “TOP MODULE” needed, I’m just going to use a simple testbench to connect it all and call it a day.

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