VR16 CPU Home Page

Assembler 🔗

Well as the name suggests, this explains how the assembler works hehe.

assembler.py 🔗

• Lines are first loaded onto a list from the asm source file.
• Based on the opcode, a simple if condition is run and the proper extractor() is chosen.
• Opcodes are only checked once the assembler reads start:, similarly exits the operation on seeing end:.
• Once the extractor runs, the output is further sent back from extractor.py to this file and they’re written onto the .mem file

extractor.py 🔗

• This file holds all functions based on opcode.
• Essentially substrings the list given by assembler.py and converts into string representation of binary.
• This is further sent back and written into the .mem file.

baseclass.py 🔗

• Holds custom exceptions by subclassing Exception.
• RegisterNotPresent and OpcodeNotPresent are two custom exceptions present at the moment.

VR-ASM Documention 🔗

This is subject to change.

General Introduction 🔗

1. All programs must start with the start: keyword.
2. Once start is initiliased, all instructions must be indented with spaces of 4.
3. All lines must end with the ; semicolon. This only applies to code once initialised.
4. Comments can made using the --.
5. Everything must be in lowercase.
6. All programs must end with the end: keyword.

Instructions and their syntax 🔗

<arg> = required argument.
[arg] = optional argument.
No need to type out <> and [].

1. add, sub, mul, div:

   - <opcode> <store_at> <operand_one> <operand_two>;
   

2. addi, subi, muli, divi:

   - <opcode> <store_at> <10_bit_immediate_value>;
   

3. and, or, xor:

   - <opcode> <store_at <operand_one> <operand_two>;
   

4. not

   - not <store_at> <operand_one>;
   

5. jump: TO BE IMPLEMENTED
6. delete

   - delete <destination_register>;
   

7. halt

   - halt;
   

Registers Present 🔗

As mentioned, only 4 general purpose registers:

• r0
• r1
• r2
• r3

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