VR16 CPU Home Page

VR16-ISA v.01 🔗

THIS IS SUBJECT TO CHANGE, I’M EXPERIMENTING ENTIRELY.

Working for this 🔗

So instead of having a definite IS Format: 0000 00 00 00 00 0000, this would keep changing based on the opcode mentioned.

For this the entire ISA has to be designed.

1. ADD:
   • 0000 | 00 | 00 | 00 | 00 | xxxx
   • opcode | store_at | operand_one | operand_two | dont-care
2. ADDI:
   • 0001 | 00 | 0000000000
   • opcode | store_at | 10-bit immediate
3. SUB:
   • 0010 | 00 | 00 | 00 | 00 | xxxx
   • opcode | store_at | operand_one | operand_two | dont-care
4. SUBI:
   • 0011 | 00 | 0000000000
   • opcode | store_at | 10-bit immediate
5. MUL:
   • 0100 | 00 | 00 | 00 | 00 | xxxx
   • opcode | store_at | operand_one | operand_two | dont-care
6. MULI:
   • 0101 | 00 | 0000000000
   • opcode | store_at | 10-bit immediate
7. DIV:
   • 0110 | 00 | 00 | 00 | 00 | xxxx
   • opcode | store_at | operand_one | operand_two | dont-care
8. DIVI:
   • 0111 | 00 | 0000000000
   • opcode | store_at | 10-bit immediate
9. STOREI:
   • 1000 | 00 | 00000000
   • opcode | destination_register | 10-bit immediate
10. JUMP:
    • 1001 | 000000000000 |
    • opcode | jump_to_12_bit_address for now
11. DELETE:
    • 1010 | 00 | xxxxxxxxxx
    • opcode | destination_register | dont-care
12. AND:
    • 1011 | 00 | 00 | 00 | xxxxxx
    • opcode | store_at | operand_one | operand_two | dont-care
13. OR:
    • 1100 | 00 | 00 | 00 | xxxxxx
    • opcode | store_at | operand_one | operand_two | dont-care
14. NOT:
    • 1101 | 00 | 00 | xxxxxxxx
    • opcode | store_at | operand_one | dont-care
15. XOR:
    • 1110 | 00 | 00 | 00 | xxxxxx
    • opcode | store_at | operand_one | operand_two | dont-care
16. HALT:
    • 1111 | xxxxxxxxxxxx
    • opcode | dont-care

Kept only basic LOGIC operations as others can be done from these.

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