VR16 CPU Home Page

VR16-ISA v.0.1.1 🔗

THIS IS SUBJECT TO CHANGE, I’M EXPERIMENTING ENTIRELY.

Working for this 🔗

So instead of having a definite IS Format: 0000 00 00 00 00 0000, this would keep changing based on the opcode mentioned.

For this the entire ISA has to be designed.

1. add:
   • 0000 | 00 | 00 | 00 | 00 | xxxx
   • opcode | store_at | operand_one | operand_two | dont-care
2. addi:
   • 0001 | 00 | 0000000000
   • opcode | store_at | 10-bit immediate
3. sub:
   • 0010 | 00 | 00 | 00 | 00 | xxxx
   • opcode | store_at | operand_one | operand_two | dont-care
4. subi:
   • 0011 | 00 | 0000000000
   • opcode | store_at | 10-bit immediate
5. mul:
   • 0100 | 00 | 00 | 00 | 00 | xxxx
   • opcode | store_at | operand_one | operand_two | dont-care
6. muli:
   • 0101 | 00 | 0000000000
   • opcode | store_at | 10-bit immediate
7. div:
   • 0110 | 00 | 00 | 00 | 00 | xxxx
   • opcode | store_at | operand_one | operand_two | dont-care
8. divi:
   • 0111 | 00 | 0000000000
   • opcode | store_at | 10-bit immediate
9. jump:
   • 1001 | 000000000000 |
   • opcode | jump_to_12_bit_address for now
10. delete:
    • 1010 | 00 | xxxxxxxxxx
    • opcode | destination_register | dont-care
11. and:
    • 1011 | 00 | 00 | 00 | xxxxxx
    • opcode | store_at | operand_one | operand_two | dont-care
12. or:
    • 1100 | 00 | 00 | 00 | xxxxxx
    • opcode | store_at | operand_one | operand_two | dont-care
13. not:
    • 1101 | 00 | 00 | xxxxxxxx
    • opcode | store_at | operand_one | dont-care
14. xor:
    • 1110 | 00 | 00 | 00 | xxxxxx
    • opcode | store_at | operand_one | operand_two | dont-care
15. halt:
    • 1111 | xxxxxxxxxxxx
    • opcode | dont-care

Kept only basic LOGIC operations as others can be done from these.

Dilemma 🔗

Since the immediate operations handle the function of storei it has been removed. To replace this opcode, I’m gonna need something useful!

“What will that be?” will remain a questions for now 🗿.

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